initializing memory in VHDL -


i have piece of code:

type mem_type array (0 15) of std_logic_vector (15 downto 0);  signal mem : mem_type:= (x"269f",x"351a",x"7752",x"9152",                          x"ccd1",x"7a8b", "a429",x"5758",                          x"a325",x"bc3d",x"725d",x"b459",                          x"7264",x"e241",x"74fc",x"19bc");

i getting following error @ line initializing mem:

no array or record type can found has elements of types matching aggregate.

one of initialisation values doesn't have x before specify hex value. code trying put string 16-bit std_logic_vector, of course error.


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