caching - Calculating Effective CPI when using write-through/write-back architecture -

so i'm trying understand homework problem given instructor , i'm lost - understand concept of write-through/write-back, etc. can't figure out actual calculations needed effective cpi, give me hand? (the problem follows:

the following table provides statistics of cache particular program. known base cpi (without cache misses) 1. known memory bus bandwidth (the bandwidth transfer data between cache , memory) 4 bytes per cycle, , takes 1 cycle send address before data transfer. memory spends 10 cycles store data bus or fetch data bus. clock rate used memory , bus quarter of cpu clock rate.

data reads per 1000 instructions: 100
data writes per 1000 instructions: 150
instruction cache miss rate: 0.4%
data cache miss rate: 3%
block size in bytes: 32

the effective cpi base cpu plus cpi contribution cache misses.

the cache miss cpi sum of of instruction cache cpi , data cache cpi.

the cache miss cost cost of reading or writing memory, need that.

the cost in bus cycles 1 (for address) plus 10 (memory busy time) + 8 (32 byte blocks size divided 4 bytes/cycle) = 19 cycles. multiply 4 cpu cycles. total 76 cpu cycles.

so cost cache misses .004 * 76 = .304 cycles.

the cost d caches misses (.10 + .15) * .03 * 76 = .57 cycles

so effective cpi 1 + .304 + .57 = 1.874 cycles.